Multi-input amplifier architecture with a variable impedance stage

ABSTRACT

Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. The degeneration block can be selectively isolated from a reference potential node to improve performance.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/690,947 filed Aug. 30, 2017 and entitled “MULTI-INPUT AMPLIFIER WITHDEGENERATION SWITCHING BLOCK AND LOW LOSS BYPASS FUNCTION,” which claimspriority to U.S. Provisional Application No. 62/381,851 filed Aug. 31,2016 and entitled “MULTI-INPUT AMPLIFIER WITH DEGENERATION SWITCHINGBLOCK AND LOW LOSS BYPASS FUNCTION,” each of which is expresslyincorporated by reference herein in its entirety for all purposes.

BACKGROUND Field

The present disclosure relates to amplifiers for wireless communicationapplications.

Description of Related Art

Wireless communication devices typically include components in afront-end module that are configured to amplify received radio-frequency(RF) signals. The front-end module can include a plurality of gain modesto provide different levels of amplification.

SUMMARY

According to a number of implementations, the present disclosure relatesto a variable-gain signal amplifier that includes a variable-gain stageconfigured to receive an input signal and generate an amplified outputsignal; and a degeneration switching block coupled to the variable-gainstage and configured to provide a plurality of gain levels of thevariable-gain stage.

In some embodiments, the signal comprises a radio frequency signal. Insome embodiments, the amplifier is configured to selectively provide abypass path that bypasses the variable-gain stage and an amplificationpath that passes through the variable-gain stage.

In some embodiments, the degeneration switching block is furtherconfigured to provide tailored impedances to the variable gain stage. Infurther embodiments, the tailored impedances are configured to provideimproved linearity in the amplified output signal relative to a variablegain stage that is not coupled to the degeneration switching block withthe tailored impedances. In further embodiments, the degenerationswitching block is configured to provide a first tailored impedance fora first gain level of the plurality of gain levels and a second tailoredimpedance for a second gain level of the plurality of gain levels. Inyet further embodiments, the first tailored impedance is greater thanthe second tailored impedance and the first gain level is less than thesecond gain level.

In some embodiments, the amplifier also includes a control circuitconfigured to generate an amplification control signal to control thevariable-gain stage and the degeneration switching circuit. In furtherembodiments, the control circuit is configured to provide a plurality ofamplification control signals corresponding to the plurality of gainlevels.

In some embodiments, the amplifier further includes a medium gain modefeedback block coupled to an input of the variable-gain stage, themedium gain mode configured to provide feedback to the variable-gainstage for a subset of the plurality of gain levels. In furtherembodiments, the medium gain mode feedback block and the degenerationswitching block provide improved linearity to the amplified outputsignal relative to an amplifier without the medium gain feedback blockand the degeneration switching block.

In some embodiments, the amplifier further includes a bypass blockcoupled to an input of the variable gain stage, the bypass blockconfigured to be activated in a low gain level of the plurality of gainlevels to provide a bypass path that does not include the variable-gainstage. In further embodiments, the bypass path does not include thedegeneration switching block.

In some embodiments, the amplifier further includes a cascode buffercoupled to an output of the variable-gain stage. In some embodiments,the amplifier further includes a plurality of input nodes coupled to thevariable-gain stage. In further embodiments, the amplifier is configuredto receive a plurality of input signals at the plurality of input nodes,individual received signals having frequencies within different signalfrequency bands. In yet further embodiments, the amplifier is configuredto amplify signals received at individual input ports independent ofamplification of other received signals.

According to a number of implementations, the present disclosure relatesto a degeneration switching circuit that includes a variable-impedancestage coupled to a signal amplifier having various gain levels andconfigured to provide various impedance values associated with thevarious gain levels; and a switch operatively associated with thevariable-impedance stage and implemented to selectively isolate thevariable-impedance stage from a reference potential node.

In some embodiments, the signal amplifier is configured to amplify radiofrequency signals. In some embodiments, a bypass path provided in thecircuit bypasses the variable-impedance stage.

In some embodiments, the various impedance values are configured toprovide improved linearity of the signal amplifier relative to a signalamplifier that is not coupled to the degeneration switching circuit withthe various impedance values associated with the various gain levels. Infurther embodiments, the variable-impedance stage is configured toprovide a first tailored impedance value for a first gain level of thevarious gain levels and a second tailored impedance value for a secondgain level of the various gain levels.

In some embodiments, the circuit further includes a control circuitconfigured to generate an amplification control signal to control thevariable-impedance stage and the switch. In further embodiments, thecontrol circuit is configured to provide a plurality of amplificationcontrol signals corresponding to the various gain levels.

According to a number of implementations, the present disclosure relatesto a front end architecture that includes a variable gain signalamplifier including a variable-gain stage configured to receive an inputsignal and generate an amplified output signal and a degenerationswitching block coupled to the variable-gain stage and configured toprovide a plurality of gain levels of the variable-gain stage. The frontend architecture also includes a filter assembly coupled to the variablegain signal amplifier to direct frequency bands to select inputs of thevariable gain signal amplifier. The front end architecture also includesa controller implemented to control the variable gain signal amplifierto provide a plurality of gain modes such that, in a low gain mode, thevariable gain signal amplifier directs signals along a path thatbypasses the variable-gain stage.

In some embodiments, the degeneration switching block is furtherconfigured to provide tailored impedances to the variable-gain stage. Infurther embodiments, the tailored impedances are configured to provideimproved linearity in the amplified output signal relative to a variablegain stage that is not coupled to the degeneration switching block withthe tailored impedances. In further embodiments, the degenerationswitching block is configured to provide a first tailored impedance fora first gain level of the plurality of gain levels and a second tailoredimpedance for a second gain level of the plurality of gain levels.

According to a number of implementations, the present disclosure relatesto a wireless device that includes a diversity antenna and a filterassembly coupled to the diversity antenna to receive signals and todirect frequency bands along select paths. The wireless device alsoincludes a variable gain signal amplifier including a variable-gainstage configured to receive an input signal and generate an amplifiedoutput signal and a degeneration switching block coupled to thevariable-gain stage and configured to provide a plurality of gain levelsof the variable-gain stage. The wireless device also includes acontroller implemented to control the variable gain signal amplifier toprovide a plurality of gain modes such that, in a low gain mode, thevariable gain signal amplifier directs signals along a path thatbypasses the variable-gain stage.

In some embodiments, the degeneration switching block is furtherconfigured to provide tailored impedances to the variable-gain stage. Infurther embodiments, the tailored impedances are configured to provideimproved linearity in the amplified output signal relative to a variablegain stage that is not coupled to the degeneration switching block withthe tailored impedances. In further embodiments, the degenerationswitching block is configured to provide a first tailored impedance fora first gain level of the plurality of gain levels and a second tailoredimpedance for a second gain level of the plurality of gain levels.

For purposes of summarizing the disclosure, certain aspects, advantagesand novel features have been described herein. It is to be understoodthat not necessarily all such advantages may be achieved in accordancewith any particular embodiment. Thus, the disclosed embodiments may becarried out in a manner that achieves or optimizes one advantage orgroup of advantages as taught herein without necessarily achieving otheradvantages as may be taught or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a wireless device having a primary antenna and adiversity antenna.

FIG. 2 illustrates a diversity receiver (DRx) configuration including aDRx front-end module (FEM).

FIG. 3A illustrates an example variable gain amplifier configurationthat includes a multi-input gain stage configured to receive multipleinputs and to selectively amplify the received signals with the gainstage or to provide a bypass path through a bypass block.

FIG. 3B illustrates another example variable gain amplifier thatincludes the same components as the variable gain amplifier of FIG. 3A,with the addition of certain elements.

FIG. 3C illustrates another example variable gain amplifier that issimilar to the variable gain amplifier of FIG. 3A, with the removal ofthe bypass switch.

FIG. 3D illustrates another example variable gain amplifier thatincludes the same components as the variable gain amplifier of FIG. 3C,with the addition of certain elements.

FIG. 4 illustrates a variable-gain signal amplifier that includes avariable-gain stage configured to receive an input signal and togenerate an amplified output signal.

FIG. 5 illustrates a degeneration switching circuit that includes avariable-impedance stage coupled to a signal amplifier having variousgain levels.

FIG. 6 illustrates an example variable gain amplifier configuration thatis configured similarly to the variable gain amplifier of FIG. 3B.

FIGS. 7A, 7B, and 7C illustrate examples of operating modes of thevariable gain signal amplifier configuration of FIG. 6.

FIG. 8 illustrates a variable gain signal amplifier that is similar tothe variable gain signal amplifier configuration of FIG. 6, but with thebypass switch removed.

FIG. 9 illustrates a variable gain signal amplifier that is similar tothe variable gain signal amplifier configuration of FIG. 6, but with ashutdown switch block instead of the medium gain mode feedback module.

FIG. 10 illustrates a variable gain signal amplifier 1010 that issimilar to the variable gain signal amplifier configuration of FIG. 9,but with the bypass switch removed.

FIG. 11 shows that in some embodiments, some or all of the diversityreceiver configurations can be implemented, wholly or partially, in amodule.

FIG. 12 shows that in some embodiments, some or all of the diversityreceiver configurations can be implemented, wholly or partially, in anarchitecture.

FIG. 13 illustrates an example wireless device having one or moreadvantageous features described herein.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The headings provided herein, if any, are for convenience only and donot necessarily affect the scope or meaning of the claimed invention.

Overview

FIG. 1 illustrates a wireless device 100 having a primary antenna 160and a diversity antenna 170. The wireless device 100 includes an RFmodule 106 and a transceiver 104 that may be controlled by a controller102. The transceiver 104 is configured to convert between analog signals(e.g., radio-frequency (RF) signals) and digital data signals. To thatend, the transceiver 104 may include a digital-to-analog converter, ananalog-to-digital converter, a local oscillator for modulating ordemodulating a baseband analog signal to or from a carrier frequency, abaseband processor that converts between digital samples and data bits(e.g., voice or other types of data), or other components.

The RF module 106 is coupled between the primary antenna 160 and thetransceiver 104. Because the RF module 106 may be physically close tothe primary antenna 160 to reduce attenuation due to cable loss, the RFmodule 106 may be referred to as front-end module (FEM). The RF module106 may perform processing on an analog signal received from the primaryantenna 160 for the transceiver 104 or received from the transceiver 104for transmission via the primary antenna 160. To that end, the RF module106 may include filters, power amplifiers, low noise amplifiers, bandselect switches, attenuators, matching circuits, and other components.

When a signal is transmitted to the wireless device 100, the signal maybe received at both the primary antenna 160 and the diversity antenna170. The primary antenna 160 and diversity antenna 170 may be physicallyspaced apart such that the signal at the primary antenna 160 anddiversity antenna 170 is received with different characteristics. Forexample, in one embodiment, the primary antenna 160 and the diversityantenna 170 may receive the signal with different attenuation, noise,frequency response, and/or phase shift. The transceiver 104 may use bothof the signals with different characteristics to determine data bitscorresponding to the signal. In some implementations, the transceiver104 selects from between the primary antenna 160 and the diversityantenna 170 based on the characteristics, such as selecting the antennawith the highest signal-to-noise ratio. In some implementations, thetransceiver 104 combines the signals from the primary antenna 160 andthe diversity antenna 170 to increase the signal-to-noise ratio of thecombined signal. In some implementations, the transceiver 104 processesthe signals to perform multiple-input/multiple-output (MiMo)communication.

In some embodiments, the diversity antenna 170 is configured to receivesignals within multiple cellular frequency bands and/or wireless localarea network (WLAN) frequency bands. In such embodiments, the wirelessdevice 100 can include a multiplexer, switching network, and/or filterassembly coupled to the diversity antenna 170 that is configured toseparate the diversity signal into different frequency ranges. Forexample, the multiplexer can be configured to include a low pass filterthat passes a frequency range that includes low band cellularfrequencies, a bandpass filter that passes a frequency range thatincludes low band WLAN signals and mid-band and high-band cellularsignals, and a high pass filter that passes a frequency range thatincludes high-band WLAN signals. This example is merely for illustrativepurpose. As another example, the multiplexer can have a variety ofdifferent configurations such as a diplexer that provides thefunctionality of a high pass filter and a low pass filter.

Because the diversity antenna 170 is physically spaced apart from theprimary antenna 160, the diversity antenna 170 can be coupled to thetransceiver 104 by a transmission line, such as a cable or a printedcircuit board (PCB) trace. In some implementations, the transmissionline is lossy and attenuates the signal received at the diversityantenna 170 before it reaches the transceiver 104. Thus, in someimplementations, gain is applied to the signal received at the diversityantenna 170. The gain (and other analog processing, such as filtering)may be applied by the diversity receiver module 108. Because such adiversity receiver module 108 may be located physically close to thediversity antenna 170, it may be referred to a diversity receiverfront-end module, examples of which are described in greater detailherein.

The RF module 106 and the diversity receiver module 108 include variablegain amplifiers 110 a, 110 b configured to provide a plurality of gainmodes to amplify signals from the primary antenna 160 and the diversityantenna 170, respectively. Each variable gain amplifier 110 a, 110 b caninclude a gain stage 120 and a degeneration switching block 130 thatchanges inductance based at least in part on a gain mode of the variablegain amplifier 110 a, 110 b. Signals received at the variable gainamplifiers 110 a, 110 b can be amplified using the gain stage 120 or thesignals can be allowed to bypass the gain stage 120, as described ingreater detail herein. The selected inductance of the degenerationswitching block 130, the bypass path, and/or the gain mode of thevariable gain amplifier 110 a, 110 b can be controlled by the controller102. The degeneration switching block 130 can be configured to changeinductance to increase performance of the variable gain amplifier 110 a,110 b relative to an amplifier with fixed inductance. Performance can beincreased by increasing linearity and/or by reducing noise introducedduring amplification, for example. The variable gain amplifier 110 a,110 b can receive multiple input signals and output a single signal or aplurality of output signals. In certain implementations, individualinputs can have corresponding individual degeneration switching blocksto improve input isolation between input ports.

Advantageously, the architecture of the variable gain amplifier 110 a,110 b can provide for multi-input processing without the use of aswitch. The variable gain amplifier 110 a, 110 b can advantageouslyachieve targeted or improved linearity by using a switchabledegeneration block with tailored inductances. The variable gainamplifier 110 a, 110 b can provide targeted or improved input to outputisolation through the use of a shunt switch in the bypass path. Thevariable gain amplifier 110 a, 110 b can provide a low-loss directbypass mode in particular gain modes, such as a low gain mode.

The controller 102 can be configured to generate and/or send controlsignals to other components of the wireless device 100. In someembodiments, the controller 102 provides signals based at least in parton specifications provided by the mobile industry processer interfacealliance (MIPI® Alliance). The controller 102 can be configured toreceive signals from other components of the wireless device 100 toprocess to determine control signals to receive to other components. Insome embodiments, the controller 102 can be configured to analyzesignals or data to determine control signals to send to other componentsof the wireless device 100. The controller 102 can be configured togenerate control signals based on gain modes provided by the wirelessdevice 100. For example, the controller 102 can send control signals tothe variable gain amplifiers 110 a, 110 b to control the gain mode.Similarly, the controller 102 can be configured to generate controlsignals to select inductances of the degeneration switching block 130.The controller can be configured to generate control signals to controlthe variable gain amplifier 110 a, 110 b to provide a bypass path.

In some implementations, the controller 102 generates amplifier controlsignal(s) based on a quality of service metric of an input signalreceived at the input. In some implementations, the controller 102generates the amplifier control signal(s) based on a signal receivedfrom a communications controller, which may, in turn, be based on aquality of service (QoS) metric of the received signal. The QoS metricof the received signal may be based, at least in part, on the diversitysignal received on the diversity antenna 170 (e.g., an input signalreceived at the input). The QoS metric of the received signal may befurther based on a signal received on a primary antenna 160. In someimplementations, the controller 102 generates the amplifier controlsignal(s) based on a QoS metric of the diversity signal withoutreceiving a signal from the communications controller. In someimplementations, the QoS metric includes a signal strength. As anotherexample, the QoS metric may include a bit error rate, a data throughput,a transmission delay, or any other QoS metric. In some implementations,the controller 102 controls the gain (and/or current) of the amplifiersin the variable gain amplifiers 110 a, 110 b. In some implementations,the controller 102 controls the gain of other components of the wirelessdevice based on an amplifier control signal.

In some implementations, the variable gain amplifiers 110 a, 110 b mayinclude a step-variable gain amplifier configured to amplify receivedsignals with a gain of one of a plurality of configured amountsindicated by an amplifier control signal. In some implementations, thevariable gain amplifiers 110 a, 110 b may include acontinuously-variable gain amplifier configured to amplify receivedsignals with a gain proportional to or dictated by the amplifier controlsignal. In some implementations, the variable gain amplifiers 110 a, 110b may include a step-variable current amplifier configured to amplifyreceived signals by drawing a current of one of plurality of configuredamounts indicated by the amplifier control signal. In someimplementations, the variable gain amplifiers 110 a, 110 b may include acontinuously-variable current amplifier configured to amplify receivedsignals by drawing a current proportional to the amplifier controlsignal.

FIG. 2 illustrates a diversity receiver (DRx) configuration 200including a DRx front-end module (FEM) 208. The DRx configuration 200includes a diversity antenna 170 that is configured to receive adiversity signal and provide the diversity signal to the DRx FEM 150through a filter assembly 272. The filter assembly 272 can include amultiplexer, for example, that is configured to selectively directsignals within targeted frequency ranges along respective paths to amulti-input amplifier 220 that is coupled to a degeneration switchingcircuit 230. The signals can be radio frequency (RF) signals thatinclude, for example and without limitation, cellular signals (e.g.,low-, mid-, high- and/or ultra-high-band cellular frequencies), WLANsignals, BLUETOOTH® signals, GPS signals, and the like.

The DRx FEM 208 is configured to perform processing on the diversitysignals received from the filter assembly 272. For example, the DRx FEM208 may be configured to filter the diversity signals to one or moreactive frequency bands that can include cellular and/or WLAN frequencybands. The controller 102 can be configured to control the DRx FEM 208to selectively direct signals to targeted filters to accomplish thefiltering. As another example, the DRx FEM 208 may be configured toamplify one or more of the filtered signals using the amplifier 220. Tothat end, the DRx FEM 208 may include filters, low-noise amplifiers,band select switches, matching circuits, and other components. Thecontroller 102 can be configured to interact with components in the DRxFEM 208 to intelligently select paths for the diversity signals throughthe DRx FEM 208.

The DRx FEM 208 transmits at least a portion of the processed diversitysignals to the transceiver 104. The transceiver 104 may be controlled bythe controller 102. In some implementations, the controller 102 may beimplemented within the transceiver 104.

The DRx FEM 208 can be configured to provide a plurality of gain modes.For the plurality of gain modes, different inductances can be providedby a variable impedance stage 232 of the degeneration switching circuit230. In one or more gain modes, a switch 234 of the variable impedancestage 232 can be configured to select an impedance (e.g., an inductance)that is coupled to the amplifier 220. This can be done to improvelinearity of the amplification process, for example. These selectableimpedances can be embedded onto a multi-input amplifier architecture.

In some embodiments, utilization of selectable impedances coupled to anamplification stage, e.g., an LNA, can provide improved linearity and/orIIP3. The variable impedance stage 232 with the switch 234 canbeneficially allow the amplifier 220 to be coupled to a desired ortargeted impedance for particular gain modes and/or signal amplitudes.In some embodiments, the DRx configuration 200 is configured to bypassamplification when operating in a low gain mode and to amplify signalswith the amplifier 220 when operating in other gain modes. This canadvantageously allow the DRx configuration 200 to improve linearity inparticular gain modes.

In some embodiments, the amplifier 220 is configured to receive aplurality of input signals and provide a single output signal. Incertain embodiments, the amplifier 220 can be configured to receive aplurality of input signals and provide a corresponding plurality ofoutput signals. The filter assembly 272 can be configured to directsignals corresponding to particular frequency bands along designatedpaths to the amplifier 220. In certain implementations, the amplifier220 can provide different gain modes for the received signals. Thevariable impedance stage 232 can select different impedances using theswitch 234 to couple to the amplifier 220, the selected impedances basedat least in part on the gain mode of the amplifier 220. In certainimplementations, the amplifier 220 can operate in a bypass configurationsuch that the signal passes through a bypass path and in anamplification configuration such that the signal passes through anamplification path with a selected impedance provided by the variableimpedance stage 232. This can advantageously allow the DRx FEM 208 toprovide variable gain and/or a plurality of gain modes while reducingthe negative impacts on linearity (e.g., IIP3) and/or noise factor (NF)relative to configurations that do not selectively provide bypass pathsand/or variable impedances. The amplifier 220 can include any suitableamplifier circuit configured to provide a desired or targetedamplification. In some embodiments, the amplifier 220 includes alow-noise amplifier (LNA) circuit configured to amplify signals from aplurality of frequency bands (e.g., cellular frequency bands and/or WLANfrequency bands) received at a plurality of inputs, or a multi-inputLNA. However, it is to be understood that the embodiments describedherein are not to be limited to implementations that utilize low-noiseamplifiers but include implementations that use any of a variety ofamplifiers.

The amplifier 220 can be configured to amplify signals based at least inpart on a plurality of gain modes. For example, the amplifier 220 can beconfigured to provide a first amplification or gain for a first gainmode, a second amplification or gain for a second gain mode, and so on.The amplifier 220 can be controlled by the controller 102 to control thegain provided at the amplifier 220. For example, the controller 102 canprovide a signal indicative of a desired or targeted gain to theamplifier 220 and the amplifier 220 can provide the targeted gain. Thecontroller 102 may receive an indication of the targeted gain fromanother component in a wireless device, for example, and control theamplifier 220 based at least in part on that indication. Similarly, thedegeneration switching circuit 230 can be controlled based at least inpart on a gain mode and/or targeted gain of the amplifier 220.

The controller 102 can be configured to control the DRx FEM 208 toselectively provide tailored impedances. For example, the controller 102and the DRx FEM 208 can control the variable impedance stage 232 toconfigure the switch 234 to provide a targeted impedance based at leastin part on a gain mode. As another example, the controller 102 and theDRx FEM 208 can control the amplifier to provide a bypass path based atleast in part on a gain mode. As another example, the controller 102 andthe DRx FEM 208 can use the amplifier 220 to provide a plurality of gainmodes.

Example Architectures of Variable Gain Amplifiers

Front end modules generally include amplifiers such as low-noiseamplifiers (LNAs) to amplify received signals. In wireless devices thatprovide a variety of gain modes, it may be advantageous to selectivelyprovide variable or tailored impedance at a gain stage to improveperformance. Similarly, for at least one gain mode, it may beadvantageous to bypass a gain stage to improve performance (e.g.,improve linearity).

Accordingly, provided herein are variable gain amplifiers thatselectively provide variable or tailored impedances at a degenerationblock and/or feedback block depending at least in part on a gain mode ofthe variable gain amplifier. This advantageously reduces or eliminatesperformance penalties in one or more gain modes. Furthermore, thevariable impedances can be configured to improve linearity of theamplification process in targeted gain modes. Similarly, the variablegain amplifier can be configured to provide a low-loss bypass mode in alow gain mode to improve signal quality.

FIG. 3A illustrates an example variable gain amplifier configuration 310a that includes a multi-input gain stage 312 configured to receivemultiple inputs and to selectively amplify the received signals with thegain stage 320 or to provide a bypass path through a bypass block 340.The gain stage 320 is coupled to a degeneration switching block 330 thatis configured to selectively provide tailored impedances based at leastin part on a gain mode of the variable gain amplifier configuration 310a. In certain implementations, the multi-input gain stage 312 isconfigured to receive multiple signals at distinct input ports, eachdistinct input port configured to receive signals at one or moreparticular cellular frequency bands. For example, a signal in a firstband can be received at a first input port, a signal in a second bandcan be received at a second input port, and a signal in a third band canbe received at a third input port.

The variable gain amplifier 310 a can be configured to providemulti-input processing without the use of a switching network. Thevariable gain amplifier 310 a can be configured to achieve relativelyhigh linearity through the use of the degeneration switching block 330.In certain implementations, the bypass block 340 includes a shunt switchthat can provide high input to output isolation relative toconfigurations without such a switch. The variable gain amplifier 310 acan be configured to provide a low-loss direct bypass mode by directingsignals from the input through the bypass block 340 and not the gainstage 320. The low-loss direct bypass mode can be implemented in a lowgain mode, for example.

The variable gain amplifier 310 a includes the multi-input gain stage312 that provides a voltage to current gain stage 320. The multi-inputgain stage 312 can be configured to provide isolation between inputs. Insome embodiments, the variable gain amplifier 310 a can include adegeneration switching block 330 for each input to further isolate theinputs.

The degeneration switching block 330 is configured to provide impedanceto the gain stage 320 input. This can improve performance by providingpower and/or noise matching with prior stages in the processing chain.The degeneration switching block 330 can be configured to improvelinearity of the gain stage 320 by providing a feedback mechanism. Insome embodiments, the degeneration switching block 330 is configured toprovide a first impedance for a first gain mode and a second impedancefor a second gain mode. The selected impedances provided by thedegeneration switching block 330 can also be configured to improvelinearity of the gain stage 320. The variable gain amplifier 310 a canbe configured to bypass the degeneration switching block 330 in a bypassmode. This can improve linearity performance by reducing or minimizingleakage current passing through the gain stage 320.

The bypass block 340 is configured to receive signals from the multipleinputs and to provide a path to the output that does not pass throughthe gain stage 320 or the degeneration switching block 330. The bypassblock 340 can include components that serve to isolate the input andoutput in one or more of the gain modes provided by the variable gainamplifier 310 a.

The medium gain mode feedback block 350 a is configured to be activatedfor a subset of the gain modes provided by the variable gain amplifier310 a. The medium gain mode feedback block 350 a is configured toprovide targeted impedances for the input signals. This can help toimprove linearity of the amplification process. The medium gain modefeedback block 350 a can also be configured to control feedback withinthe variable gain amplifier 310 a. The medium gain mode feedback block350 a can be configured to provide functionality similar to including asecond degeneration block in the circuit.

The bypass switch 360 is configured to selectively provide a path fromthe inputs through the bypass block 340 to the output or a path from theinputs through the gain stage 320 to the output. The bypass switch 360can include one or more switching elements to isolate and/or to selectthe desired path based at least in part on a gain mode of the variablegain amplifier 310 a.

In certain embodiments, the variable gain amplifier 310 a can beconfigured to provide a plurality of gain modes, e.g., gain modes G0,G1, . . . , GN with G0 being the highest gain and GN being a bypassmode. When operating in gain mode GN, the variable gain amplifier 310 acan be configured to direct signals from the inputs to the bypass block340. When operating in gain modes G0 to GN-1, the variable gainamplifier 310 a can be configured to direct signals through the gainstage 320 and to activate the degeneration switching block 330. Thedegeneration switching block 330 can be configured to provide differentimpedance levels for individual gain modes or for groups of gain modes.Even in these gain modes, the bypass block 340 may be at least partiallyactivated by activating a shunt switch in the bypass block 340 toprovide isolation between the inputs and the output. The variable gainamplifier 310 a can be configured to activate the medium gain modefeedback block 350 a for one or more of the gain modes G0 to GN-1

The variable gain signal amplifier 310 a can be configured to achieverelatively low noise and high linearity (e.g., higher IIP3) relative toamplifiers without the disclosed medium gain mode feedback block 350 a,bypass block 340, and degeneration switching block 330. The variablegain signal amplifier 310 a can be configured to amplify radio frequency(RF) signals such as cellular signals, WLAN signals, BLUETOOTH® signals,GPS signals, and the like. The variable gain signal amplifier 310 a canbe configured to provide broadband capabilities by receiving signalsover a plurality of frequency bands at the multiple inputs andprocessing these signals. The variable gain signal amplifier 310 a canbe configured to independently process signals at the respective inputs.The variable gain signal amplifier 310 a can be configured to becontrolled by a control circuit assembly, such as a controller (e.g.,the controller 102 described herein with reference to FIGS. 1 and 2).The control circuit assembly can intelligently and selectively switchpaths between an amplification path and a bypass path and canselectively provide impedances with the degeneration switching block330.

It is to be understood that although three inputs are illustrated, thevariable gain amplifier 310 a can include any suitable number of inputs.For example and without limitation, the variable gain amplifier 310 acan include at least 2 inputs, at least 4 inputs, at least 8 inputs, atleast 16 inputs, at least 32 inputs, at least 64 inputs, or at least anynumber of inputs in the described ranges. As another example and withoutlimitation, the variable gain amplifier 310 a can include less than orequal to 64 inputs, less than or equal to 32 inputs, less than or equalto 16 inputs, less than or equal to 8, less than or equal to 4 inputs,or less than or equal to any number of inputs in the described ranges.

FIG. 3B illustrates another example variable gain amplifier 310 b thatincludes the same components as the variable gain amplifier 310 a ofFIG. 3A, with the addition of certain elements. For example, thevariable gain amplifier 310 b includes matching networks 313, 318, and345. The input matching network 313 is configured to provide impedancematching for the signals received at the inputs. The output matchingnetwork 318 is similarly configured to provide impedance matching for anoutput load 316 and the amplifier comprising the gain stage 320 and acascode buffer 314. The bypass matching network 345 similarly providesimpedance matching for the bypass block 340. For the matching networks313, 318, 345, any suitable combination of inductors and capacitors canbe used to provide the targeted impedances.

The variable gain amplifier 310 b also includes the output load 316 andcascode buffer 314 as part of the amplification chain. The cascodebuffer 314 can be configured to act as a current buffer. The cascodebuffer 314 is configured to provide isolation between the gain stage 320and the output. The cascode buffer 314 can also be configured to improvethe gain of the variable gain amplifier 310 b.

The output load 316 is configured to provide a load to current togenerate an output voltage swing. The output load 316 can be configuredto be tuned or tunable for each band received at the inputs. The outputload 316 can be configured to improve return loss and/or increasebandwidth by tailoring the resistance of the output load 316. Thevoltage VDD can be configured to set the gain mode of the variable gainamplifier 310 b. For example, the voltage VDD can be configured so thata lower current flowing through the output load 316 corresponds to alower gain of the variable gain amplifier 310 b.

FIG. 3C illustrates another example variable gain amplifier 310 c thatis similar to the variable gain amplifier 310 a of FIG. 3A, with theremoval of the bypass switch 360. Without the bypass switch 360, theoutput of the bypass block 340 is coupled to the output of the output ofthe gain stage 320. Furthermore, the medium gain mode feedback block isreplaced with a shutdown switch block 350 c that is not coupled to theoutput as in the variable gain amplifier 310 a of FIG. 3A. Instead, theshutdown switch block 350 c is configured to selectively isolate inputnodes to reduce leakage in the amplifier 310 c. In some embodiments,this can be achieved by activating a switch between an input node and areference potential node when the input is not being used. In variousimplementations, the switch can couple the input node to a referencepotential node through a capacitive element.

FIG. 3D illustrates another example variable gain amplifier 310 d thatincludes the same components as the variable gain amplifier 310 c ofFIG. 3C, with the addition of certain elements. For example, thevariable gain amplifier 310 d includes matching networks 313, 318, and345. The input matching network 313 is configured to provide impedancematching for the signals received at the inputs. The output matchingnetwork 318 is similarly configured to provide impedance matching for anoutput load 316 and the amplifier comprising the gain stage 320 and acascode buffer 314. The bypass matching network 345 similarly providesimpedance matching for the bypass block 340. For the matching networks313, 318, 345, any suitable combination of inductors and capacitors canbe used to provide the targeted impedances.

The variable gain amplifier 310 d also includes the output load 316 andcascode buffer 314 as part of the amplification chain. The cascodebuffer 314 can be configured to act as a current buffer. The cascodebuffer 314 is configured to provide isolation between the gain stage 320and the output. The cascode buffer 314 can also be configured to improvethe gain of the variable gain amplifier 310 d. The output load 316 isconfigured to provide a load to current to generate an output voltageswing. The output load 316 can be configured to be tuned or tunable foreach band received at the inputs. The output load 316 can be configuredto improve return loss and/or increase bandwidth by tailoring theresistance of the output load 316. The voltage VDD can be configured toset the gain mode of the variable gain amplifier 310 d. For example, thevoltage VDD can be configured so that a lower current flowing throughthe output load 316 corresponds to a lower gain of the variable gainamplifier 310 d.

FIG. 4 illustrates a variable-gain signal amplifier 410 that includes avariable-gain stage 420 configured to receive an input signal and togenerate an amplified output signal. The variable-gain signal amplifier410 also includes a degeneration switching block 430 coupled to thevariable-gain stage 420. The degeneration switching block 430 can beconfigured to provide a plurality of different gain levels of thevariable-gain stage 420.

FIG. 5 illustrates a degeneration switching circuit 530 that includes avariable-impedance stage 532 coupled to a signal amplifier 520 havingvarious gain levels. The variable-impedance stage 532 can be configuredto provide various impedance values associated with the various gainlevels. The degeneration switching circuit 530 includes a switch 534operatively associated with the variable-impedance stage 532 andimplemented to selectively isolate the variable-impedance stage 532 froma reference potential node.

FIG. 6 illustrates an example variable gain amplifier configuration 610that is configured similarly to the variable gain amplifier 310 bdescribed herein with reference to FIG. 3B. The variable gain amplifier610 includes example electrical components to demonstrate an exampleimplementation of the amplifier. It is to be understood, however, thatthis is merely an illustrative example implementation and the scope ofthe disclosure extends to additional implementations encompassingsimilar architectures.

The variable gain amplifier configuration 610 includes a multi-inputgain stage 612 configured to receive inputs A, B, and C and toselectively amplify the received signals with corresponding transistorsQ3, Q4, and Q5 in conjunction with the cascode buffer 614 with thetransistor Q10. The multi-input gain stage 612 is also configured toprovide a bypass path through a bypass block 340 that includes switchingtransistors Q6, Q7, and Q8 for the respective inputs A, B, and C.

The multi-input gain stage 612 is coupled to a degeneration switchingblock 630 that is configured to selectively provide tailored impedancesbased at least in part on a gain mode of the variable gain amplifierconfiguration 610. In certain implementations, the multi-input gainstage 612 is configured to receive multiple signals at distinct inputports, each distinct input port configured to receive signals at one ormore particular cellular frequency bands. For example, input A receivesa signal in a first band, input B receives a signal in a second band,and input C receives a signal in a third band. In some embodiments, eachof the transistors Q3, Q4, and Q5 can be coupled to a dedicateddegeneration switching block 630 to increase isolation between inputports. The inputs are coupled respectively to inductors L4, L5, and L6to provide input impedance matching.

The variable gain amplifier configuration 610 can be configured toprovide multi-input processing without the use of a switching network.The variable gain amplifier configuration 610 can be configured toachieve relatively high linearity through the use of the degenerationswitching block 630. In certain implementations, the bypass block 640includes a shunt switch Q9 that can provide high input to outputisolation relative to configurations without such a switch. The variablegain amplifier configuration 610 can be configured to provide a low-lossdirect bypass mode by directing signals from the inputs through thebypass block 640. The low-loss direct bypass mode can be implemented ina low gain mode, for example.

The variable gain amplifier configuration 610 includes the multi-inputgain stage 612 that provides a voltage to current gain stage comprisingthe transistors Q3-Q5. The multi-input gain stage 612 is configured toprovide a voltage to current gain stage. Further, the multi-input gainstage 612 is configured to amplify respective input signals inconjunction with the cascode buffer 614 that includes the transistorQ10, the cascode buffer 614 configured to acts as a current buffer tolower input impedance and increase output impedance.

The degeneration switching block 630 is configured to provide impedanceto the gain stage of the multi-input gain stage 612. This can improveperformance by providing power and/or noise matching with prior stagesin the processing chain. The degeneration switching block 630 can beconfigured to improve linearity of the gain stage (e.g., transistorsQ3-Q5) by providing a feedback mechanism. The degeneration switchingblock 630 can be configured to provide a first impedance L1 for a firstgain mode and a second impedance provided by L1 and L2 for a second gainmode by respectively activating the transistor Q2 and the transistor Q1.The selected impedances provided by the degeneration switching block 630can also be configured to improve linearity of the gain stage. Thevariable gain amplifier configuration 610 can be configured to bypassthe degeneration switching block 630 in a bypass mode. This can improvelinearity performance by reducing or minimizing leakage current passingthrough the gain stage. In certain implementations, the degenerationswitching block 630 can be configured to provide a lower inductance forhigher gain modes. The amount of inductance provided by the degenerationswitching block 630 can change with changes in gain mode of the variablegain amplifier configuration 610.

The bypass block 640 is configured to receive signals from the multipleinputs and to provide a path to the output that does not pass throughthe gain stage (e.g., transistors Q3-Q5) or the degeneration switchingblock 630. The bypass block 640 is configured to provide a single pathto the output through transistor Q11 and capacitor C1. The capacitor C1can be configured to block direct current (DC) voltages from an outputsupply. The bypass block 640 also includes a shunt switch throughtransistor Q9 that selectively couples the bypass block 640 to areference potential node to aid in isolating the inputs from the output.A bypass matching network 645 can provide additional impedance matchingflexibility.

The medium gain mode feedback block 650 is configured to be activatedfor a subset of the gain modes provided by the variable gain amplifierconfiguration 610. The medium gain mode feedback block 650 is configuredto provide targeted impedances for the input signals. This can help toimprove linearity of the amplification process. An RC matching network651 can be used to control the amount of feedback in the system.Furthermore, the RC matching network 651 can be configured to functionas a block for DC voltages. The RC matching network 651 can beconfigured to control feedback behavior in amplitude and phase. The RCmatching network 651 can include a capacitor, a resistor, a capacitorand resistor in series, or any suitable combination of capacitors,resistors, and other components. The medium gain mode feedback block 650can also be configured to control feedback within the variable gainamplifier 610. The medium gain mode feedback block 650 can be configuredto provide functionality similar to including a second degenerationblock in the circuit.

When activated, signals from respective inputs A, B, and C enter themedium gain feedback block 650 at points A, B, and C and exit the blockat point D. This point D is coupled to the circuit prior to an outputmatching network 618 and a bypass switch 660. In other words, the mediumgain mode feedback block 650 couples the respective inputs A, B, and Cto the output through transistors Q14-Q16 and Q18. The additionaltransistor Q17 can be configured to provide a shunt switch to areference potential node, similar to the bypass block 640. The point Dcan be positioned prior to the output matching network 618, within theoutput matching network 618, or after the output matching network 618.Because the medium gain mode feedback block 650 can be configured togenerate a cancellation between the input and the output, the point Dcan be positioned within the variable gain amplifier configuration 610to improve performance.

The bypass switch 660 is configured to selectively provide a path fromthe inputs A, B, and C through the bypass block 640 to the output or apath from the inputs A, B, and C through the gain stage and amplifierelements (e.g., the cascode buffer 614 and the output matching network618) to the output. The bypass switch 660 includes a transistor Q12 thatcontrols connection of an amplification path to the output and atransistor Q13 that controls connection of a bypass path to the output.The bypass switch 660 can be controlled based at least in part on a gainmode of the variable gain amplifier 610.

The matching networks 618 and 645 can include any suitable combinationof inductors and capacitors can be used to provide the targetedimpedances. The output matching network 618 is configured to provideimpedance matching for an output load 616 and the amplifier comprisingthe gain stage (e.g., transistors Q3-Q5) and the cascode buffer 614. Thebypass matching network 645 similarly provides impedance matching forthe bypass block 640.

The variable gain amplifier 610 includes the output load 616 and cascodebuffer 614 as part of the amplification path. The cascode buffer 614includes the transistor Q10 that is configured to act as a currentbuffer. The cascode buffer 614 is configured to provide isolationbetween the gain stage and the output. The cascode buffer 614 can alsobe configured to improve the gain of the variable gain amplifier 610.The output load 616 is configured to provide a load to current togenerate an output voltage swing. The output load 616 can be configuredto be tuned or tunable for each band received at the inputs. Forexample, the output load includes a variable capacitor C2 that can betuned for particular cellular frequency bands. The output load 616 canalso be configured to improve return loss and/or increase bandwidth bytailoring the resistance R1 of the output load 616.

The voltage VDD can be configured to set the gain mode of the variablegain amplifier 610. For example, the voltage VDD can be configured sothat a lower current flowing through the output load 616 corresponds toa lower gain of the variable gain amplifier 610.

FIGS. 7A-7C illustrate examples of operating modes of the variable gainsignal amplifier configuration 610 of FIG. 6. FIG. 7A illustratesoperation in one or more high gain modes. In these high gain modes, thebypass block 640 is deactivated, except for the shunt switch Q9. Signalsreceived at the inputs A, B, and C are directed through the gain stagecomprising transistors Q3-Q5 and through the cascode buffer 614 to theoutput through the output matching network 618 and the bypass switch660. The bypass switch activates Q12 and deactivates Q13 in these highgain modes. Furthermore, the transistor Q2 is on and the transistor Q1is off in these high gain modes so that the inductance provided to thegain stage through the degeneration switching block 630 is L1. Themedium gain mode feedback block 650 is also deactivated in these highgain modes.

FIG. 7B illustrates operation in one or more medium gain modes. Thesemodes may also be referred to as low-gain, high-linearity modes. Inthese medium gain modes, operation is similar to the operation of theone or more high gain modes with notable differences. First, transistorQ2 is off and the transistor Q1 is on in the degeneration block 630 sothat the inductance provided to the gain stage through the degenerationswitching block 630 is provided by both L1 and L2. Thus, increasedimpedance is provided for lower gain modes, or, decreased impedance isprovided for higher gain modes. Second, the medium gain mode feedbackblock 650 is activated. This provides additional feedback to thecircuit, similar to adding a second degeneration block.

FIG. 7C illustrates operation in one or more low gain modes. In theselow gain modes, the bypass block 640 is activated and the gain stagetransistors Q3-Q5 are deactivated. Signals received at the inputs A, B,and C are directed through the bypass block 640 to the output throughthe bypass matching network 645 and the bypass switch 660. The bypassswitch activates Q13 and deactivates Q12 in these low gain modes.Furthermore, the transistors Q1 and Q2 are off to deactivate thedegeneration switching block 630 to improve linearity performance byreducing or minimizing leakage current through the gain stagetransistors Q3-Q5. The medium gain mode feedback block 650 is alsodeactivated in these low gain modes.

FIG. 8 illustrates a variable gain signal amplifier 810 that is similarto the variable gain signal amplifier configuration 610 of FIG. 6, butwith the bypass switch 660 removed. With the removal of the bypassswitch, the output of the bypass matching network 645 instead couples toan input node of the output matching network 618. In this configuration,there is no bypass switch to control selection of an amplification pathor a bypass path. Rather, the selected transistors of the gain stage(e.g., transistors Q3-Q5) and of the bypass block (e.g., transistorsQ6-Q8) are selectively activated and deactivated to provide the bypasspath or the amplification path.

FIG. 9 illustrates a variable gain signal amplifier 910 that is similarto the variable gain signal amplifier configuration 610 of FIG. 6, butwith a shutdown switch block 950 instead of a medium gain mode feedbackmodule. In this configuration, the point D is removed because theshutdown switch block 950 does not couple to the amplification path atan output node of the output matching network 618. Instead, the shutdownswitch block 950 includes transistors Q14-Q16 and capacitors C3-05configured to selectively isolate the input nodes A, B, and C. In someembodiments, the shutdown switch block 950 does not include thecapacitors C3-05. The shutdown switch block 950 can be configured toturn a switch on (e.g., activate a transistor) when a correspondinginput is not in use. This can be done to shut off that input to groundto reduce or eliminate leakage in the amplifier configuration.

FIG. 10 illustrates a variable gain signal amplifier 1010 that issimilar to the variable gain signal amplifier configuration 910 of FIG.9, but with the bypass switch 660 removed. As with the variable gainsignal amplifier 810 of FIG. 8, the removal of the bypass switch resultsin the output of the bypass matching network 645 being coupled to aninput node of the output matching network 618. In this configuration,there is no bypass switch to control selection of an amplification pathor a bypass path. Rather, the selected transistors of the gain stage(e.g., transistors Q3-Q5) and of the bypass block (e.g., transistorsQ6-Q8) are selectively activated and deactivated to provide the bypasspath or the amplification path.

Examples of Products and Architectures

FIG. 11 shows that in some embodiments, some or all of the diversityreceiver configurations, including some or all of the diversity receiverconfigurations having combinations of features (e.g., FIGS. 1-10), canbe implemented, wholly or partially, in a module. Such a module can be,for example, a front-end module (FEM). Such a module can be, forexample, a diversity receiver (DRx) FEM. Such a module can be, forexample, a multi-input, multi-output (MiMo) module.

In the example of FIG. 11, a module 1108 can include a packagingsubstrate 1101, and a number of components can be mounted on such apackaging substrate 1101. For example, a controller 1102 (which mayinclude a front-end power management integrated circuit [FE-PIMC]), acombination assembly 1106, a variable gain amplifier assembly 1110 thatincludes a gain stage 1120 and a degeneration switching block 1130having one or more features as described herein, and a filter bank 1108(which may include one or more bandpass filters) can be mounted and/orimplemented on and/or within the packaging substrate 1101. Othercomponents, such as a number of SMT devices 1105, can also be mounted onthe packaging substrate 1101. Although all of the various components aredepicted as being laid out on the packaging substrate 1101, it will beunderstood that some component(s) can be implemented over othercomponent(s).

FIG. 12 shows that in some embodiments, some or all of the diversityreceiver configurations, including some or all of the diversity receiverconfigurations having combinations of features (e.g., FIGS. 1-10), canbe implemented, wholly or partially, in an architecture. Such anarchitecture may include one or more modules, and can be configured toprovide front-end functionality such as diversity receiver (DRx)front-end functionality.

In the example of FIG. 12, an architecture 1208 can include a controller1202 (which may include a front-end power management integrated circuit[FE-PIMC]), a combination assembly 1206, a variable gain amplifierassembly 1210 that includes a gain stage 1220 and a degenerationswitching block 1230 having one or more features as described herein,and a filter bank 1208 (which may include one or more bandpass filters)can be mounted and/or implemented on and/or within the packagingsubstrate 1201. Other components, such as a number of SMT devices 1205,can also be implemented in the architecture 1208.

In some implementations, a device and/or a circuit having one or morefeatures described herein can be included in an RF electronic devicesuch as a wireless device. Such a device and/or a circuit can beimplemented directly in the wireless device, in a modular form asdescribed herein, or in some combination thereof. In some embodiments,such a wireless device can include, for example, a cellular phone, asmart-phone, a hand-held wireless device with or without phonefunctionality, a wireless tablet, etc.

FIG. 13 depicts an example wireless device 1300 having one or moreadvantageous features described herein. In the context of one or moremodules having one or more features as described herein, such modulescan be generally depicted by a dashed box 1306 (which can be implementedas, for example, a front-end module) and a diversity receiver (DRx)module 1308 (which can be implemented as, for example, a front-endmodule).

Referring to FIG. 13, power amplifiers (PAs) 1382 can receive theirrespective RF signals from a transceiver 1304 that can be configured andoperated to generate RF signals to be amplified and transmitted, and toprocess received signals. The transceiver 1304 is shown to interact witha baseband sub-system 1305 that is configured to provide conversionbetween data and/or voice signals suitable for a user and RF signalssuitable for the transceiver 1304. The transceiver 1304 can also be incommunication with a power management component 1307 that is configuredto manage power for the operation of the wireless device 1300. Suchpower management can also control operations of the baseband sub-system1305 and the modules 1306 and 1308.

The baseband sub-system 1305 is shown to be connected to a userinterface 1301 to facilitate various input and output of voice and/ordata provided to and received from the user. The baseband sub-system1305 can also be connected to a memory 1303 that is configured to storedata and/or instructions to facilitate the operation of the wirelessdevice, and/or to provide storage of information for the user.

In the example wireless device 1300, outputs of the PAs 1382 are shownto be matched (via respective match circuits 1384) and routed to theirrespective duplexers 1386. Such amplified and filtered signals can berouted to a primary antenna 1360 through a switching network 1309 fortransmission. In some embodiments, the duplexers 1386 can allow transmitand receive operations to be performed simultaneously using a commonantenna (e.g., primary antenna 1360). In FIG. 13, received signals areshown to be routed to a variable gain amplifier assembly 1310 a, whichprovides the features and benefits of the variable gain amplifiersdescribed herein. The DRx module 1308 includes a similar variable gainamplifier assembly 1310 b as well.

In the example wireless device 1300, signals received at the primaryantenna 1360 can be sent to a variable gain amplifier 1310 a in thefront end module 1306. The variable gain amplifier 1310 a can include again stage 1320 and a degeneration switching block 1330. The variablegain amplifier 1310 a is configured to receive a plurality of signals atinputs 1311 and output a plurality of processed signals at outputs 1319.The variable gain amplifier 1310 a is configured to amplify signalsbased at least in part on a gain mode and to provide targeted impedanceswith the degeneration switching block 330 based at least in part on thegain mode. This can be done to improve linearity for signals relative tovariable gain amplifiers that do not include one or more of thedescribed features. In at least one low gain mode, the gain stage 1320and the degeneration switching block 1330 can be bypassed. In at leastone non-low gain mode, additional feedback can be provided in thevariable gain amplifier 1310 a to improve linearity of the amplificationprocess, such as through a medium gain mode feedback module, asdescribed herein.

The wireless device also includes a diversity antenna 1370 and adiversity receiver module 1308 that receives signals from the diversityantenna 1370. The diversity receive module 1308 includes a variable gainamplifier 1310 b, similar to the variable gain amplifier 1310 a in thefront end module 1306. The diversity receiver module 1308 and thevariable gain amplifier 1310 b process the received signals and transmitthe processed signals to the transceiver 1304. In some embodiments, adiplexer, triplexer, or other multiplexer or filter assembly can beincluded between the diversity antenna 1370 and the diversity receivermodule 1370, as described herein.

One or more features of the present disclosure can be implemented withvarious cellular frequency bands as described herein. Examples of suchbands are listed in Table 1. It will be understood that at least some ofthe bands can be divided into sub-bands. It will also be understood thatone or more features of the present disclosure can be implemented withfrequency ranges that do not have designations such as the examples ofTable 1. It is to be understood that the term radio frequency (RF) andradio frequency signals refers to signals that include at least thefrequencies listed in Table 1.

TABLE 1 Tx Frequency Range Rx Frequency Range Band Mode (MHz) (MHz) B1FDD 1,920-1,980 2,110-2,170 B2 FDD 1,850-1,910 1,930-1,990 B3 FDD1,710-1,785 1,805-1,880 B4 FDD 1,710-1,755 2,110-2,155 B5 FDD 824-849869-894 B6 FDD 830-840 875-885 B7 FDD 2,500-2,570 2,620-2,690 B8 FDD880-915 925-960 B9 FDD 1,749.9-1,784.9 1,844.9-1,879.9 B10 FDD1,710-1,770 2,110-2,170 B11 FDD 1,427.9-1,447.9 1,475.9-1,495.9 B12 FDD699-716 729-746 B13 FDD 777-787 746-756 B14 FDD 788-798 758-768 B15 FDD1,900-1,920 2,600-2,620 B16 FDD 2,010-2,025 2,585-2,600 B17 FDD 704-716734-746 B18 FDD 815-830 860-875 B19 FDD 830-845 875-890 B20 FDD 832-862791-821 B21 FDD 1,447.9-1,462.9 1,495.9-1,510.9 B22 FDD 3,410-3,4903,510-3,590 B23 FDD 2,000-2,020 2,180-2,200 B24 FDD 1,626.5-1,660.51,525-1,559 B25 FDD 1,850-1,915 1,930-1,995 B26 FDD 814-849 859-894 B27FDD 807-824 852-869 B28 FDD 703-748 758-803 B29 FDD N/A 716-728 B30 FDD2,305-2,315 2,350-2,360 B31 FDD 452.5-457.5 462.5-467.5 B32 FDD N/A1,452-1,496 B33 TDD 1,900-1,920 1,900-1,920 B34 TDD 2,010-2,0252,010-2,025 B35 TDD 1,850-1,910 1,850-1,910 B36 TDD 1,930-1,9901,930-1,990 B37 TDD 1,910-1,930 1,910-1,930 B38 TDD 2,570-2,6202,570-2,620 B39 TDD 1,880-1,920 1,880-1,920 B40 TDD 2,300-2,4002,300-2,400 B41 TDD 2,496-2,690 2,496-2,690 B42 TDD 3,400-3,6003,400-3,600 B43 TDD 3,600-3,800 3,600-3,800 B44 TDD 703-803 703-803 B45TDD 1,447-1,467 1,447-1,467 B46 TDD 5,150-5,925 5,150-5,925 B65 FDD1,920-2,010 2,110-2,200 B66 FDD 1,710-1,780 2,110-2,200 B67 FDD N/A738-758 B68 FDD 698-728 753-783

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Additionally, the words “herein,” “above,” “below,” and words of similarimport, when used in this application, shall refer to this applicationas a whole and not to any particular portions of this application. Wherethe context permits, words in the above Description using the singularor plural number may also include the plural or singular numberrespectively. The word “or” in reference to a list of two or more items,that word covers all of the following interpretations of the word: anyof the items in the list, all of the items in the list, and anycombination of the items in the list.

The above detailed description of embodiments of the invention is notintended to be exhaustive or to limit the invention to the precise formdisclosed above. While specific embodiments of, and examples for, theinvention are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

While some embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

What is claimed is:
 1. An amplifier architecture comprising: a signalamplifier having a plurality of input nodes and an output node, thesignal amplifier configured to amplify, based on a selected gain mode ofa plurality of gain modes, an input signal received at one of theplurality of input nodes to provide an amplified output signal at theoutput node; and a degeneration switching circuit coupled to the signalamplifier, the degeneration switching circuit including a switchoperatively coupled to a variable impedance stage to selectively isolatethe variable impedance stage from a reference potential node.
 2. Thearchitecture of claim 1 wherein the variable impedance stage isconfigured to provide an impedance based on the selected gain mode. 3.The architecture of claim 1 wherein the variable impedance stage isfurther configured to provide a plurality of tailored impedances.
 4. Thearchitecture of claim 3 wherein the plurality of tailored impedances isconfigured to provide improved linearity in the amplified output signalrelative to a signal amplifier that is not coupled to the degenerationswitching circuit with the plurality of tailored impedances.
 5. Thearchitecture of claim 3 wherein the variable impedance stage isconfigured to provide a first tailored impedance for a first gain modeof the plurality of gain modes and a second tailored impedance for asecond gain mode of the plurality of gain modes.
 6. The architecture ofclaim 5 wherein the first tailored impedance is greater than the secondtailored impedance and the second gain mode provides greateramplification than the first gain mode.
 7. The architecture of claim 1further comprising a medium gain mode feedback block coupled to theplurality of inputs of the signal amplifier, the medium gain modefeedback block configured to provide feedback to the signal amplifierfor a subset of the plurality of gain modes.
 8. The architecture ofclaim 1 wherein the signal amplifier is configured to receive aplurality of input signals at the plurality of input nodes, individualreceived signals having frequencies within different signal frequencybands.
 9. The architecture of claim 8 wherein the amplifier isconfigured to amplify signals received at individual input portsindependent of amplification of other received signals.
 10. Thearchitecture of claim 1 further comprising a shutdown switch blockcoupled to the plurality of inputs of the signal amplifier, the shutdownswitch block configured to selectively isolate input nodes of theplurality of input nodes to reduce leakage in the signal amplifier. 11.The architecture of claim 10 wherein the shutdown switch block is notcoupled to the output node.
 12. The architecture of claim 10 wherein theshutdown switch block is configured to selectively couple an input nodeof the plurality of input nodes to a reference potential node while theinput node is not in use.
 13. The architecture of claim 1 wherein theswitch of the degeneration switching circuit comprises a plurality oftransistors configured to selectively different combinations ofinductors of the variable impedance stage to the signal amplifier. 14.The architecture of claim 13 wherein each of the plurality oftransistors is configured to be off in a bypass mode of the plurality ofgain modes to isolate the variable impedance stage from the referencepotential node.
 15. A front-end module comprising: a packaging substrateconfigured to receive a plurality of components; a variable-gainamplifier assembly implemented on the packaging substrate, thevariable-gain amplifier assembly including a signal amplifier having aplurality of input nodes and an output node, the signal amplifierconfigured to amplify, based on a selected gain mode of a plurality ofgain modes, an input signal received at one of the plurality of inputnodes to provide an amplified output signal at the output node; thevariable-gain amplifier assembly also including a degeneration switchingcircuit coupled to the signal amplifier, the degeneration switchingcircuit including a switch operatively coupled to a variable impedancestage to selectively isolate the variable impedance stage from areference potential node; a filter assembly implemented on the packagingsubstrate, the filter assembly coupled to the variable-gain amplifierassembly to direct frequency bands to select inputs of the plurality ofinput nodes; and a controller implemented on the packaging substrate,the controller configured to control the variable-gain amplifierassembly to provide a plurality of gain modes such that, in a low gainmode, the switch of the degeneration switching circuit isolates thedegeneration switching circuit from the reference potential node. 16.The module of claim 15 wherein the variable impedance stage isconfigured to provide a plurality of tailored impedances to the signalamplifier.
 17. The module of claim 15 wherein the variable-gainamplifier assembly further includes a shutdown switch block coupled tothe plurality of inputs of the signal amplifier, the shutdown switchblock configured to selectively isolate input nodes of the plurality ofinput nodes to reduce leakage in the signal amplifier.
 18. The module ofclaim 15 wherein the variable-gain amplifier assembly further includes amedium gain mode feedback block coupled to the plurality of inputs ofthe signal amplifier, the medium gain mode feedback block configured toprovide feedback to the signal amplifier for a subset of the pluralityof gain modes.
 19. A wireless device comprising: a diversity antenna; afilter assembly coupled to the diversity antenna to receive signals andto direct frequency bands along select paths; a variable-gain amplifierassembly including a signal amplifier having a plurality of input nodesand an output node, the signal amplifier configured to amplify, based ona selected gain mode of a plurality of gain modes, an input signalreceived at one of the plurality of input nodes to provide an amplifiedoutput signal at the output node; the variable-gain amplifier assemblyalso including a degeneration switching circuit coupled to the signalamplifier, the degeneration switching circuit including a switchoperatively coupled to a variable impedance stage to selectively isolatethe variable impedance stage from a reference potential node; and acontroller configured to control the variable-gain amplifier assembly toprovide a plurality of gain modes such that, in a low gain mode, theswitch of the degeneration switching circuit isolates the degenerationswitching circuit from the reference potential node.
 20. The device ofclaim 19 wherein the variable impedance stage is configured to provide aplurality of tailored impedances to the signal amplifier.